The present invention relates to a method of manufacturing a semiconductor device and semiconductor device technology. More particularly, it relates to technology which is effectively applicable to a DC/DC converter.
A DC/DC converter widely used as a power supply circuit has a configuration in which a power MOSFET for a high-side switch and a power MOSFET for a low-side switch are connected in series. The power MOSFET for a high-side switch has a switching function for controlling the DC/DC converter. The power MOSFET for a low-side switch has a switching function for performing synchronous rectification. The two power MOSFETs are synchronously and alternately turned on and off to carry out supply voltage conversion.
For example, a configuration in which a switching element (power MOSFET or IGBT) (6) and a control element (7) to control the switching element are contained in a same package is disclosed in Japanese Unexamined Patent Publication No. 2001-320009 (patent document 1) (see FIGS. 1 and 2). The control element (7) includes no element for a PWM (Pulse Width Modulation) circuit.
Also, a configuration in which a power switching element (power MOSFET or IGBT) (10) and a control element (11) to control the power switching element are contained in a same package is disclosed in Japanese Unexamined Patent Publication No. 2002-83927 (patent document 2) (see FIGS. 1 and 2). The control element (11) includes no element for a PWM circuit.
Furthermore, a configuration in which a power MOSFET (3) and an IC chip (4) having a control function are sealed in a same resin molded section is disclosed in Japanese Unexamined Patent Publication No. Hei 11(1999)-31775 (patent document 3) (see FIG. 1). No concrete description of the internal configuration of the IC chip (4) is provided in the patent document 3.
Still furthermore, a configuration in which power transistors (3 and 4) and a driver IC (2) to refine control signals inputted to the control terminals of the power transistors are installed in a same package is disclosed in Japanese Unexamined Patent Publication No. 2005-93762 (patent document 4) (see FIG. 1).